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? 2007 microchip technology inc. ds21952b-page 1 MCP23017/mcp23s17 features ? 16-bit remote bidi rectional i/o port - i/o pins default to input ? high-speed i 2 c? interface ( MCP23017 ) - 100 khz - 400 khz -1.7mhz ? high-speed spi interface ( mcp23s17 ) - 10 mhz (max.) ? three hardware address pins to allow up to eight devices on the bus ? configurable interrupt output pins - configurable as active-high, active-low or open-drain ? inta and intb can be configured to operate independently or together ? configurable interrupt source - interrupt-on-change from configured register defaults or pin changes ? polarity inversion register to configure the polarity of the input port data ? external reset input ? low standby current: 1 a (max.) ? operating voltage: - 1.8v to 5.5v @ -40c to +85c - 2.7v to 5.5v @ -40c to +85c - 4.5v to 5.5v @ -40c to +125c packages ? 28-pin pdip (300 mil) ? 28-pin soic (300 mil) ? 28-pin ssop ? 28-pin qfn package types qfn 2 3 4 5 6 1 7 v ss nc 15 16 17 18 19 20 21 gpa4 gpa3 gpa2 gpa1 gpa0 v dd intb scl sda nc a0 a1 a2 reset 23 24 25 26 27 28 22 gpb3 gpb2 gpb1 gpb0 gpa7 gpa6 gpa5 10 11 8 9 121314 MCP23017 gpb5 gpb6 gpb7 gpb4 inta gpb0 gpb1 gpb2 gpb3 inta gpb4 nc nc gpb5 gpb6 gpb7 scl gpa7 gpa6 gpa5 gpa4 gpa3 gpa2 gpa1 gpa0 v dd v ss a2 a1 a0 sda ? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pdip, MCP23017 intb reset ssop soic, gpb0 gpb1 gpb2 gpb3 inta gpb4 so cs gpb5 gpb6 gpb7 sck gpa7 gpa6 gpa5 gpa4 gpa3 gpa2 gpa1 gpa0 v dd v ss a2 a1 a0 si ? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 mcp23s17 intb reset mcp23s17 MCP23017 qfn 2 3 4 5 6 1 7 v ss cs 15 16 17 18 19 20 21 gpa4 gpa3 gpa2 gpa1 gpa0 v dd intb si so a0 a1 a2 reset 23 24 25 26 27 28 22 gpb3 gpb2 gpb1 gpb0 gpa7 gpa6 gpa5 10 11 8 9 121314 mcp23s17 gpb5 gpb6 gpb7 gpb4 inta sck pdip, ssop soic, 16-bit i/o expander with serial interface
MCP23017/mcp23s17 ds21952b-page 2 ? 2007 microchip technology inc. functional block diagram gpb7 gpb6 gpb5 gpb4 gpb3 gpb2 gpb1 gpb0 i 2 c? control gpio scl sda reset inta 16 configuration/ 8 a2:a0 3 control registers spi si so sck cs mcp23s17 MCP23017 gpa7 gpa6 gpa5 gpa4 gpa3 gpa2 gpa1 gpa0 intb interrupt gpio serializer/ deserializer logic decode
? 2007 microchip technology inc. ds21952b-page 3 MCP23017/mcp23s17 1.0 device overview the MCP23017/mcp23s17 (mcp23x17) device family provides 16-bit, general purpose parallel i/o expansion for i 2 c bus or spi applications. the two devices differ only in the serial interface. ? MCP23017 ? i 2 c interface ? mcp23s17 ? spi interface the mcp23x17 consists of multiple 8-bit configuration registers for input, output and polarity selection. the system master can enable the i/os as either inputs or outputs by writing the i/o co nfiguration bits (iodira/b). the data for each input or output is kept in the corresponding input or output register. the polarity of the input port register can be inverted with the polarity inversion register. all registers can be read by the system master. the 16-bit i/o port functionally consists of two 8-bit ports (porta and portb). the mcp23x17 can be configured to operate in the 8-bit or 16-bit modes via iocon.bank. there are two interrupt pins, inta and intb, that can be associated with their respective ports, or can be logically or?ed together so that both pins will activate if either port causes an interrupt. the interrupt output can be configured to activate under two conditions (mutually exclusive): 1. when any input state differs from its corresponding input port register state. this is used to indicate to t he system master that an input state has changed. 2. when an input state differs from a preconfigured register value (defval register). the interrupt capture regist er captures port values at the time of the interrupt, thereby saving the condition that caused the interrupt. the power-on reset (por) sets the registers to their default values and initializes the device state machine. the hardware address pins are used to determine the device address.
MCP23017/mcp23s17 ds21952b-page 4 ? 2007 microchip technology inc. 1.1 pin descriptions table 1-1: pinout description pin name pdip/ soic/ ssop qfn pin type function gpb0 1 25 i/o bidirectional i/o pin. can be enabled for interrupt-on-change and/or internal weak pull-up resistor. gpb1 2 26 i/o bidirectional i/o pin. can be enabled for interrupt-on-change and/or internal weak pull-up resistor. gpb2 3 27 i/o bidirectional i/o pin. can be enabled for interrupt-on-change and/or internal weak pull-up resistor. gpb3 4 28 i/o bidirectional i/o pin. can be enabled for interrupt-on-change and/or internal weak pull-up resistor. gpb4 5 1 i/o bidirectional i/o pin. can be enabled fo r interrupt-on-change and/or internal weak pull-up resistor. gpb5 6 2 i/o bidirectional i/o pin. can be enabled fo r interrupt-on-change and/or internal weak pull-up resistor. gpb6 7 3 i/o bidirectional i/o pin. can be enabled fo r interrupt-on-change and/or internal weak pull-up resistor. gpb7 8 4 i/o bidirectional i/o pin. can be enabled fo r interrupt-on-change and/or internal weak pull-up resistor. v dd 95ppower v ss 10 6 p ground nc/cs 11 7 i nc (MCP23017), chip select (mcp23s17) scl/sck 12 8 i serial clock input sda/si 13 9 i/o serial data i/o (MCP23017), serial data input (mcp23s17) nc/so 14 10 o nc (MCP23017), serial data out (mcp23s17) a0 15 11 i hardware address pin. must be externally biased. a1 16 12 i hardware address pin. must be externally biased. a2 17 13 i hardware address pin. must be externally biased. reset 18 14 i hardware reset. must be externally biased. intb 19 15 o interrupt output for portb. can be conf igured as active-high, active-low or open-drain. inta 20 16 o interrupt output for porta. can be conf igured as active-high, active-low or open-drain. gpa0 21 17 i/o bidirectional i/o pin. can be enabled for interrupt-on-change and/or internal weak pull-up resistor. gpa1 22 18 i/o bidirectional i/o pin. can be enabled for interrupt-on-change and/or internal weak pull-up resistor. gpa2 23 19 i/o bidirectional i/o pin. can be enabled for interrupt-on-change and/or internal weak pull-up resistor. gpa3 24 20 i/o bidirectional i/o pin. can be enabled for interrupt-on-change and/or internal weak pull-up resistor. gpa4 25 21 i/o bidirectional i/o pin. can be enabled for interrupt-on-change and/or internal weak pull-up resistor. gpa5 26 22 i/o bidirectional i/o pin. can be enabled for interrupt-on-change and/or internal weak pull-up resistor. gpa6 27 23 i/o bidirectional i/o pin. can be enabled for interrupt-on-change and/or internal weak pull-up resistor. gpa7 28 24 i/o bidirectional i/o pin. can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
? 2007 microchip technology inc. ds21952b-page 5 MCP23017/mcp23s17 1.2 power-on reset (por) the on-chip por circuit holds the device in reset until v dd has reached a high enough voltage to deactivate the por circuit (i.e., release the device from reset). the maximum v dd rise time is specified in section 2.0 ?electrical characteristics? . when the device exits the por condition (releases reset), device operating parameters (i.e., voltage, temperature, serial bus frequency, etc.) must be met to ensure proper operation. 1.3 serial interface this block handles the functionality of the i 2 c (MCP23017) or spi (mcp23s17) interface protocol. the mcp23x17 contains 22 individual registers (11 register pairs) that can be addressed through the serial interface block, as shown in table 1-2 . table 1-2: register addresses 1.3.1 byte mode and sequential mode the mcp23x17 family has the ability to operate in byte mode or sequential mode (iocon.seqop). byte mode disables automatic address pointer incrementing. when operating in byte mode, the mcp23x17 family does not increment its internal address counter after each byte during the data transfer. this gives the ability to continually access the same address by providing extra clocks (without additional control bytes). this is useful for polling the gpio register for data changes or for continually writing to the output latches. a special mode (byte mode with iocon.bank = 0 ) causes the address pointer to toggle between associated a/b register pair s. for example, if the bank bit is cleared and the address pointer is initially set to address 12h (gpioa) or 13h (gpiob), the pointer will toggle between gpioa and gpiob. note that the address pointer can initially point to either address in the register pair. sequential mode enables automatic address pointer incrementing. when operating in sequential mode, the mcp23x17 family increments its address counter after each byte during the data transfer. the address pointer automatically rolls over to address 00h after accessing the last register. these two modes are not to be confused with single writes/reads and continuous writes/reads that are serial protocol sequences. for example, the device may be configured for byte mode and the master may perform a continuous read. in this case, the mcp23x17 would not increment the address pointer and would repeatedly drive data from the same location. 1.3.2 i 2 c interface 1.3.2.1 i 2 c write operation the i 2 c write operation includes the control byte and register address sequence, as shown in the bottom of figure 1-1 . this sequence is followed by eight bits of data from the master and an acknowledge (ack) from the MCP23017. the operation is ended with a stop (p) or restart (sr) condition being generated by the master. data is written to the MCP23017 after every byte transfer. if a stop or restart condition is generated during a data transfer, the data will not be written to the MCP23017. both ?byte writes? and ?sequential writes? are supported by the mcp230 17. if sequential mode is enabled (iocon, seqop = 0 ) (default), the MCP23017 increments its address counter after each ack during the data transfer. address iocon.bank = 1 address iocon.bank = 0 access to: 00h 00h iodira 10h 01h iodirb 01h 02h ipola 11h 03h ipolb 02h 04h gpintena 12h 05h gpintenb 03h 06h defvala 13h 07h defvalb 04h 08h intcona 14h 09h intconb 05h 0ah iocon 15h 0bh iocon 06h 0ch gppua 16h 0dh gppub 07h 0eh intfa 17h 0fh intfb 08h 10h intcapa 18h 11h intcapb 09h 12h gpioa 19h 13h gpiob 0ah 14h olata 1ah 15h olatb
MCP23017/mcp23s17 ds21952b-page 6 ? 2007 microchip technology inc. 1.3.2.2 i 2 c read operation i 2 c read operations include the control byte sequence, as shown in the bottom of figure 1-1 . this sequence is followed by another control byte (including the start condition and ack) with the r/w bit set (r/w = 1 ). the MCP23017 then transmits the data contained in the addressed register. the sequence is ended with the master generating a stop or restart condition. 1.3.2.3 i 2 c sequential write/read for sequential operations (write or read), instead of transmitting a stop or restart condition after the data transfer, the master clocks th e next byte pointed to by the address pointer (see section 1.3.1 ?byte mode and sequential mode? for details regarding sequential operation control). the sequence ends with the master sending a stop or restart condition. the MCP23017 address pointer will roll over to address zero after reaching the last register address. refer to figure 1-1 . 1.3.3 spi interface 1.3.3.1 spi write operation the spi write operation is started by lowering cs . the write command (slave address with r/w bit cleared) is then clocked into the device. the opcode is followed by an address and at least one data byte. 1.3.3.2 spi read operation the spi read operation is started by lowering cs . the spi read command (slave address with r/w bit set) is then clocked into the device. the opcode is followed by an address, with at least one data byte being clocked out of the device. 1.3.3.3 spi sequential write/read for sequential operations, instead of deselecting the device by raising cs , the master clocks the next byte pointed to by the address pointer. (see section 1.3.1 ?byte mode and sequential mode? for details regarding sequential operation control). the sequence ends by the raising of cs . the mcp23s17 address pointer will roll over to address zero after reaching the last register address.
? 2007 microchip technology inc. ds21952b-page 7 MCP23017/mcp23s17 figure 1-1: MCP23017 i 2 c? device protocol s p sr w r op addr d out d in - start - restart - stop - write - read - device opcode - device register address - data out from MCP23017 - data in to MCP23017 s p sr w r op addr d in d in .... s p w r op addr d out d out .... p sr w op d in d in .... p p sr r d out d out .... p op d out d out .... p sr op d in .... p op d in s p w op addr d in d in .... byte and sequential write s w op sr r op d out d out .... p byte and sequential read s w op addr d in p s w op sr r op d out p byte sequential byte sequential
MCP23017/mcp23s17 ds21952b-page 8 ? 2007 microchip technology inc. 1.4 hardware address decoder the hardware address pins are used to determine the device address. to address a device, the correspond- ing address bits in the control byte must match the pin state. the pins must be biased externally. 1.4.1 addressing i 2 c devices (MCP23017) the MCP23017 is a slave i 2 c interface device that supports 7-bit slave addressing, with the read/write bit filling out the control byte . the slave address contains four fixed bits and three user-defined hardware address bits (pins a2, a1 and a0). figure 1-2 shows the control byte format. 1.4.2 addressing spi devices (mcp23s17) the mcp23s17 is a slave spi device. the slave address contains four fixed bits and three user-defined hardware address bits (if enabled via iocon.haen) (pins a2, a1 and a0) with the read/write bit filling out the control byte. figure 1-3 shows the control byte format. the address pins should be externally biased even if disabled (iocon.haen = 0 ). figure 1-2: i 2 c? control byte format figure 1-3: spi control byte format figure 1-4: i 2 c? addressing registers figure 1-5: spi addressing registers s 0 1 0 0 a2a1a0r/w ack start bit slave address r/w bit ack bit control byte r/w = 0 = write r/w = 1 = read 0 1 0 0 a2 a1 a0 r/w slave address r/w bit control byte r/w = 0 = write r/w = 1 = read cs s0100a2a1a00 ack * a7 a6 a5 a4 a3 a2 a1 a0 ack * device opcode register address r/w = 0 *the acks are provided by the MCP23017. 0100a2 * a1 * a0 * r/wa7a6a5a4a3a2a1a0 device opcode register address cs * address pins are enabled/disabled via iocon.haen.
? 2007 microchip technology inc. ds21952b-page 9 MCP23017/mcp23s17 1.5 gpio port the gpio module is a general purpose, 16-bit wide, bidirectional port that is fu nctionally split into two 8-bit wide ports. the gpio module contains the data ports (gpion), internal pull-up resistors and the output latches (olatn). reading the gpion register reads the value on the port. reading the olatn register only reads the latches, not the actual value on the port. writing to the gpion register actually causes a write to the latches (olatn). writing to the olatn register forces the associated output drivers to drive to the level in olatn. pins configured as inputs turn off the associated output driver and put it in high-impedance. table 1-3: summary of registers associ ated with the gpio ports (bank = 1 ) table 1-4: summary of registers associ ated with the gpio ports (bank = 0 ) register name address (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 por/rst value iodira 00 io7 io6 io5 io4 io3 io2 io1 io0 1111 1111 ipola 01 ip7 ip6 ip5 ip4 ip3 ip2 ip1 ip0 0000 0000 gpintena 02 gpint7 gpint6 gpint5 gpint4 gpint3 gpint2 gpint1 gpint0 0000 0000 gppua 06 pu7 pu6 pu5 pu4 pu3 pu2 pu1 pu0 0000 0000 gpioa 09 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 0000 0000 olata 0a ol7 ol6 ol5 ol4 ol3 ol2 ol1 ol0 0000 0000 iodirb 10 io7 io6 io5 io4 io3 io2 io1 io0 1111 1111 ipolb 11 ip7 ip6 ip5 ip4 ip3 ip2 ip1 ip0 0000 0000 gpintenb 12 gpint7 gpint6 gpint5 gpint4 gpint3 gpint2 gpint1 gpint0 0000 0000 gppub 16 pu7 pu6 pu5 pu4 pu3 pu2 pu1 pu0 0000 0000 gpiob 19 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 0000 0000 olatb 1a ol7 ol6 ol5 ol4 ol3 ol2 ol1 ol0 0000 0000 register name address (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 por/rst value iodira 00 io7 io6 io5 io4 io3 io2 io1 io0 1111 1111 iodirb 01 io7 io6 io5 io4 io3 io2 io1 io0 1111 1111 ipola 02 ip7 ip6 ip5 ip4 ip3 ip2 ip1 ip0 0000 0000 ipolb 03 ip7 ip6 ip5 ip4 ip3 ip2 ip1 ip0 0000 0000 gpintena 04 gpint7 gpint6 gpint5 gpint4 gpint3 gpint2 gpint1 gpint0 0000 0000 gpintenb 05 gpint7 gpint6 gpint5 gpint4 gpint3 gpint2 gpint1 gpint0 0000 0000 gppua 0c pu7 pu6 pu5 pu4 pu3 pu2 pu1 pu0 0000 0000 gppub 0d pu7 pu6 pu5 pu4 pu3 pu2 pu1 pu0 0000 0000 gpioa 12 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 0000 0000 gpiob 13 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 0000 0000 olata 14 ol7 ol6 ol5 ol4 ol3 ol2 ol1 ol0 0000 0000 olatb 15 ol7 ol6 ol5 ol4 ol3 ol2 ol1 ol0 0000 0000
MCP23017/mcp23s17 ds21952b-page 10 ? 2007 microchip technology inc. 1.6 configuration and control registers there are 21 registers a ssociated with the mcp23x17, as shown in ta b l e 1 - 5 and ta b l e 1 - 6 . the two tables show the register mapping with the two bank bit values. ten registers are associated with porta and ten are associated with portb. one register (iocon) is shared between the two ports. the porta registers are identical to the portb regist ers, therefore, they will be referred to without differentiating between the port designation (i.e., they will not have the ?a? or ?b? designator assigned) in the register tables. table 1-5: control register summary (iocon.bank = 1 ) register name address (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 por/rst value iodira 00 io7 io6 io5 io4 io3 io2 io1 io0 1111 1111 ipola 01 ip7 ip6 ip5 ip4 ip3 ip2 ip1 ip0 0000 0000 gpintena 02 gpint7 gpint6 gpint5 gpint4 gpint3 gpint2 gpint1 gpint0 0000 0000 defvala 03 def7 def6 def5 def4 def3 def2 def1 def0 0000 0000 intcona 04 ioc7 ioc6 ioc5 ioc4 ioc3 ioc2 ioc1 ioc0 0000 0000 iocon 05 bank mirror seqop disslw haen odr intpol ? 0000 0000 gppua 06 pu7 pu6 pu5 pu4 pu3 pu2 pu1 pu0 0000 0000 intfa 07 int7 int6 int5 int4 int3 int2 int1 into 0000 0000 intcapa 08 icp7 icp6 icp5 icp4 icp3 icp2 icp1 icp0 0000 0000 gpioa 09 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 0000 0000 olata 0a ol7 ol6 ol5 ol4 ol3 ol2 ol1 ol0 0000 0000 iodirb 10 io7 io6 io5 io4 io3 io2 io1 io0 1111 1111 ipolb 11 ip7 ip6 ip5 ip4 ip3 ip2 ip1 ip0 0000 0000 gpintenb 12 gpint7 gpint6 gpint5 gpint4 gpint3 gpint2 gpint1 gpint0 0000 0000 defvalb 13 def7 def6 def5 def4 def3 def2 def1 def0 0000 0000 intconb 14 ioc7 ioc6 ioc5 ioc4 ioc3 ioc2 ioc1 ioc0 0000 0000 iocon 15 bank mirror seqop disslw haen odr intpol ? 0000 0000 gppub 16 pu7 pu6 pu5 pu4 pu3 pu2 pu1 pu0 0000 0000 intfb 17 int7 int6 int5 int4 int3 int2 int1 into 0000 0000 intcapb 18 icp7 icp6 icp5 icp4 icp3 icp2 icp1 icp0 0000 0000 gpiob 19 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 0000 0000 olatb 1a ol7 ol6 ol5 ol4 ol3 ol2 ol1 ol0 0000 0000
? 2007 microchip technology inc. ds21952b-page 11 MCP23017/mcp23s17 table 1-6: control register summary (iocon.bank = 0 ) register name address (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 por/rst value iodira 00 io7 io6 io5 io4 io3 io2 io1 io0 1111 1111 iodirb 01 io7 io6 io5 io4 io3 io2 io1 io0 1111 1111 ipola 02 ip7 ip6 ip5 ip4 ip3 ip2 ip1 ip0 0000 0000 ipolb 03 ip7 ip6 ip5 ip4 ip3 ip2 ip1 ip0 0000 0000 gpintena 04 gpint7 gpint6 gpint5 gpint4 gpint3 gpint2 gpint1 gpint0 0000 0000 gpintenb 05 gpint7 gpint6 gpint5 gpint4 gpint3 gpint2 gpint1 gpint0 0000 0000 defvala 06 def7 def6 def5 def4 def3 def2 def1 def0 0000 0000 defvalb 07 def7 def6 def5 def4 def3 def2 def1 def0 0000 0000 intcona 08 ioc7 ioc6 ioc5 ioc4 ioc3 ioc2 ioc1 ioc0 0000 0000 intconb 09 ioc7 ioc6 ioc5 ioc4 ioc3 ioc2 ioc1 ioc0 0000 0000 iocon 0a bank mirror seqop disslw haen odr intpol ? 0000 0000 iocon 0b bank mirror seqop disslw haen odr intpol ? 0000 0000 gppua 0c pu7 pu6 pu5 pu4 pu3 pu2 pu1 pu0 0000 0000 gppub 0d pu7 pu6 pu5 pu4 pu3 pu2 pu1 pu0 0000 0000 intfa 0e int7 int6 int5 int4 int3 int2 int1 into 0000 0000 intfb 0f int7 int6 int5 int4 int3 int2 int1 into 0000 0000 intcapa 10 icp7 icp6 icp5 icp4 icp3 icp2 icp1 icp0 0000 0000 intcapb 11 icp7 icp6 icp5 icp4 icp3 icp2 icp1 icp0 0000 0000 gpioa 12 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 0000 0000 gpiob 13 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 0000 0000 olata 14 ol7 ol6 ol5 ol4 ol3 ol2 ol1 ol0 0000 0000 olatb 15 ol7 ol6 ol5 ol4 ol3 ol2 ol1 ol0 0000 0000
MCP23017/mcp23s17 ds21952b-page 12 ? 2007 microchip technology inc. 1.6.1 i/o direction register controls the direction of the data i/o. when a bit is set, the corresponding pin becomes an input. when a bit is clear, the corresponding pin becomes an output. register 1-1: iodir ? i/o direction register (addr 0x00) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 io7 io6 io5 io4 io3 io2 io1 io0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 io7:io0: these bits control the direction of data i/o <7:0> 1 = pin is configured as an input. 0 = pin is configured as an output.
? 2007 microchip technology inc. ds21952b-page 13 MCP23017/mcp23s17 1.6.2 input polarity register this register allows the user to configure the polarity on the corresponding gpio port bits. if a bit is set, the corresp onding gpio register bit will reflect the inverted value on the pin. register 1-2: ipol ? input polarity port register (addr 0x01) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ip7 ip6 ip5 ip4 ip3 ip2 ip1 ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 ip7:ip0: these bits control the polarity inversion of the input pins <7:0> 1 = gpio register bit will reflect the opposite logic state of the input pin. 0 = gpio register bit will reflect the same logic state of the input pin.
MCP23017/mcp23s17 ds21952b-page 14 ? 2007 microchip technology inc. 1.6.3 interrupt-on-change control register the gpinten register controls the interrupt-on- change feature for each pin. if a bit is set, the corresponding pin is enabled for interrupt-on-change. the defval and intcon registers must also be conf igured if any pins are enabled for interrupt-on-change. register 1-3: gpinten ? interrupt-on-change pins (addr 0x02) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gpint7 gpint6 gpint5 gpint4 gpint3 gpint2 gpint1 gpint0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 gpint7:gpint0: general purpose i/o interrupt-on-change bits <7:0> 1 = enable gpio input pin for interrupt-on-change event. 0 = disable gpio input pin for interrupt-on-change event. refer to intcon and gpinten.
? 2007 microchip technology inc. ds21952b-page 15 MCP23017/mcp23s17 1.6.4 default compare register for interrupt-on-change the default comparison va lue is configured in the defval register. if enabled (via gpinten and intcon) to compare against the defval register, an opposite value on the associated pin will cause an interrupt to occur. register 1-4: defval ? default value register (addr 0x03) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 def7 def6 def5 def4 def3 def2 def1 def0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 def7:def0: these bits set the compare value for pins configured for interrupt-on-change from defaults <7:0>. refer to intcon. if the associated pin level is the opposite from the register bit, an interrupt occurs. refer to intcon and gpinten.
MCP23017/mcp23s17 ds21952b-page 16 ? 2007 microchip technology inc. 1.6.5 interrupt control register the intcon register controls how the associated pin value is compared for the interrupt-on-change feature. if a bit is set, the corresponding i/o pin is compared against the associated bit in the defval register. if a bit value is clear, the corresponding i/o pin is compared against the previous value. register 1-5: intcon ? interrupt-on -change control register (addr 0x04) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ioc7 ioc6 ioc5 ioc4 ioc3 ioc2 ioc1 ioc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 ioc7:ioc0: these bits control how the associated pin value is compared for interrupt-on-change <7:0> 1 = controls how the associated pin value is compared for interrupt-on-change. 0 = pin value is compared against the previous pin value. refer to intcon and gpinten.
? 2007 microchip technology inc. ds21952b-page 17 MCP23017/mcp23s17 1.6.6 configuration register the iocon register contains several bits for configuring the device: the bank bit changes how the registers are mapped (see table 1-5 and ta b l e 1 - 6 for more details). ? if bank = 1 , the registers associated with each port are segregated. regi sters associated with porta are mapped from address 00h - 0ah and registers associated with portb are mapped from 10h - 1ah. ? if bank = 0 , the a/b registers are paired. for example, iodira is mapped to address 00h and iodirb is mapped to the next address (address 01h). the mapping for all registers is from 00h - 15h. it is important to take care when changing the bank bit as the address mapping changes after the byte is clocked into the device. th e address pointer may point to an invalid location after the bit is modified. for example, if the device is configured to automatically increment its internal address pointer, the following scenario would occur: ? bank = 0 ? write 80h to address 0ah (iocon) to set the bank bit ? once the write completes, the internal address now points to 0bh which is an invalid address when the bank bit is set. for this reason, it is advis ed to only perform byte writes to this register when changing the bank bit. the mirror bit controls how the inta and intb pins function with respect to each other. ? when mirror = 1 , the intn pins are functionally or?ed so that an interrupt on either port will cause both pins to activate. ? when mirror = 0 , the int pins are separated. interrupt conditions on a port will cause its respective int pin to activate. the sequential operation ( seqop ) controls the incrementing function of the address pointer. if the address pointer is disabled, the address pointer does not automatically increment after each byte is clocked during a serial transfer. this feature is useful when it is desired to continuously poll (read) or modify (write) a register. the slew rate ( disslw ) bit controls the slew rate function on the sda pin. if enabled, the sda slew rate will be controlled when driving from a high to low. the hardware address enable ( haen ) bit enables/ disables hardware addressing on the mcp23s17 only. the address pins (a2, a1 and a0) must be externally biased, regardless of the haen bit value. if enabled (haen = 1 ), the device?s hardware address matches the address pins. if disabled (haen = 0 ), the device?s hardware address is a2 = a1 = a0 = 0 . the open-drain ( odr ) control bit enables/disables the int pin for open-drain configuration. erasing this bit overrides the intpol bit. the interrupt polarity ( intpol ) sets the polarity of the int pin. this bit is functional only when the odr bit is cleared, configuring the int pin as active push-pull.
MCP23017/mcp23s17 ds21952b-page 18 ? 2007 microchip technology inc. register 1-6: iocon ? i/o expander co nfiguration register (addr 0x05) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 bank mirror seqop disslw haen odr intpol ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 bank: controls how the registers are addressed 1 = the registers associated with each port are separated into different banks 0 = the registers are in the same bank (addresses are sequential) bit 6 mirror: int pins mirror bit 1 = the int pins are internally connected 0 = the int pins are not connected. inta is associ ated with porta and intb is associated with portb bit 5 seqop: sequential operation mode bit. 1 = sequential operation disabled, address pointer does not increment. 0 = sequential operation enabled, address pointer increments. bit 4 disslw: slew rate control bit for sda output. 1 = slew rate disabled. 0 = slew rate enabled. bit 3 haen: hardware address enable bit (mcp23s17 only). address pins are always enabled on MCP23017. 1 = enables the mcp23s17 address pins. 0 = disables the mcp23s17 address pins. bit 2 odr: this bit configures the in t pin as an open-drain output. 1 = open-drain output (overrides the intpol bit). 0 = active driver output (i ntpol bit sets the polarity). bit 1 intpol: this bit sets the polarity of the int output pin. 1 = active-high. 0 = active-low. bit 0 unimplemented: read as ? 0 ?.
? 2007 microchip technology inc. ds21952b-page 19 MCP23017/mcp23s17 1.6.7 pull-up resistor configuration register the gppu register controls the pull-up resistors for the port pins. if a bit is set and the corresponding pin is configured as an input, the corresponding port pin is internally pulled up with a 100 k resistor. register 1-7: gppu ? gpio pull-u p resistor register (addr 0x06) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pu7 pu6 pu5 pu4 pu3 pu2 pu1 pu0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 pu7:pu0: these bits control the weak pull-up resistor s on each pin (when configured as an input) <7:0>. 1 = pull-up enabled. 0 = pull-up disabled.
MCP23017/mcp23s17 ds21952b-page 20 ? 2007 microchip technology inc. 1.6.8 interrupt flag register the intf register reflects the interrupt condition on the port pins of any pin that is enabled for interrupts via the gpinten register. a ?set? bit indicates that the associated pin caused the interrupt. this register is ?read-only?. writes to this register will be ignored. register 1-8: intf ? interrupt flag register (addr 0x07) r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 int7 int6 int5 int4 int3 int2 int1 int0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 int7:int0: these bits reflect the interrupt condition on the port. will reflect the change only if interrupts are enabled (gpinten) <7:0>. 1 = pin caused interrupt. 0 = interrupt not pending.
? 2007 microchip technology inc. ds21952b-page 21 MCP23017/mcp23s17 1.6.9 interrupt capture register the intcap register captures the gpio port value at the time the interrupt occurr ed. the register is ?read only? and is updated only when an interrupt occurs. the register will remain unc hanged until the interrupt is cleared via a read of intcap or gpio. register 1-9: intcap ? interrupt captured value for port register (addr 0x08) r-x r-x r-x r-x r-x r-x r-x r-x icp7 icp6 icp5 icp4 icp3 icp2 icp1 icp0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 icp7:icp0: these bits reflect the logic level on the port pi ns at the time of interrupt due to pin change <7:0> 1 = logic-high. 0 = logic-low.
MCP23017/mcp23s17 ds21952b-page 22 ? 2007 microchip technology inc. 1.6.10 port register the gpio register reflects the value on the port. reading from this register reads the port. writing to this register modifies the out put latch (olat) register. register 1-10: gpio ? general purp ose i/o port register (addr 0x09) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 gp7:gp0: these bits reflect the logic level on the pins <7:0> 1 = logic-high. 0 = logic-low.
? 2007 microchip technology inc. ds21952b-page 23 MCP23017/mcp23s17 1.6.11 output latch register (olat) the olat register provides access to the output latches. a read from this register results in a read of the olat and not the port itself . a write to this register modifies the output latches that modifies the pins configured as outputs. register 1-11: olat ? output latch register 0 (addr 0x0a) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ol7 ol6 ol5 ol4 ol3 ol2 ol1 ol0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 ol7:ol0: these bits reflect the logic level on the output latch <7:0> 1 = logic-high. 0 = logic-low.
MCP23017/mcp23s17 ds21952b-page 24 ? 2007 microchip technology inc. 1.7 interrupt logic if enabled, the mcp23x17 activates the intn interrupt output when one of the port pins changes state or when a pin does not match the preconfigured default. each pin is individually configurable as follows: ? enable/disable interrupt via gpinten ? can interrupt on either pin change or change from default as configured in defval both conditions are referred to as interrupt-on-change (ioc). the interrupt control module uses the following registers/bits: ? iocon.mirror ? controls if the two interrupt pins mirror each other ? gpinten ? interrupt enable register ? intcon ? controls the source for the ioc ? defval ? contains the register default for ioc operation 1.7.1 inta and intb there are two interrupt pins: inta and intb. by default, inta is associated with gpan pins (porta) and intb is associated with gpbn pins (portb). each port has an independent signal which is cleared if its associated gpio or intcap register is read. 1.7.1.1 mirroring the int pins additionally, the intn pins can be configured to mirror each other so that any inte rrupt will cause both pins to go active. this is controlled via iocon.mirror. if iocon.mirror = 0 , the internal signals are routed independently to the inta and intb pads. if iocon.mirror = 1 , the internal signals are or?ed together and routed to the intn pads. in this case, the interrupt will only be cleared if the associated gpio or intcap is read (see table 1-7 ). table 1-7: interrupt operation (iocon.mirror = 1 ) 1.7.2 ioc from pin change if enabled, the mcp23x17 will generate an interrupt if a mismatch condition exists between the current port value and the previous port value. only ioc enabled pins will be compared. refer to register 1-3 and register 1-5 . 1.7.3 ioc from register default if enabled, the mcp23x17 will generate an interrupt if a mismatch occurs between the defval register and the port. only ioc enabled pins will be compared. refer to register 1-3 , register 1-5 and register 1-4 . 1.7.4 interrupt operation the intn interrupt output can be configured as active- low, active-high or open-drain via the iocon register. only those pins that are configured as an input (iodir register) with interrupt-on-change (ioc) enabled (iointen register) can cause an interrupt. pins defined as an output have no effect on the interrupt output pin. input change activity on a port input pin that is enabled for ioc will generate an internal device interrupt and the device will capture the va lue of the port and copy it into intcap. the interrupt will remain active until the intcap or gpio register is read. writing to these registers will not affect the interrupt. the interrupt condition will be cleared after the lsb of the data is clocked out during a read command of gpio or intcap. the first interrupt event will cause the port contents to be copied into the intcap register. subsequent interrupt conditions on the port will not cause an interrupt to occur as long as the interrupt is not cleared by a read of intcap or gpio. interrupt condition read portn * interupt result gpioa porta clear portb unchanged gpiob porta unchanged portb clear gpioa and gpiob porta unchanged portb unchanged both porta and portb clear * port n = gpion or intcapn note: the value in intcap can be lost if gpio is read before intcap while another ioc is pending. after reading gpio, the interrupt will clear and then set due to the pending ioc, causing the intcap register to update.
? 2007 microchip technology inc. ds21952b-page 25 MCP23017/mcp23s17 1.7.5 interrupt conditions there are two possible configurations that cause interrupts (configured via intcon): 1. pins configured for interrupt-on-pin change will cause an interrupt to occur if a pin changes to the opposite state. th e default state is reset after an interrupt occurs and after clearing the interrupt condition (i.e ., after reading gpio or intcap). for example, an interrupt occurs by an input changing from ? 1 ? to ? 0 ?. the new initial state for the pin is a logic 0 after the interrupt is cleared. 2. pins configured for interrupt-on- change from register value will cause an interrupt to occur if the corresponding input pin differs from the register bit. the interrupt condition will remain as long as the condition exists, regardless if the intcap or gpio is read. see figure 1-6 and figure 1-7 for more information on interrupt operations. figure 1-6: interrupt-on-pin change figure 1-7: interrupt-on-change from register default gpx int active active port value is captured into intcap read gpio or intcap port value is captured into intcap int port value is captured into intcap read gpiu or intcap defval register x x x x x 0 x x gp2 76543210 gp: active active (int clears only if interrupt condition does not exist.) pin pin
MCP23017/mcp23s17 ds21952b-page 26 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21952b-page 27 MCP23017/mcp23s17 2.0 electrical characteristics absolute maximum ratings ? ambient temperature under bias................................................................................................. ............ -40c to +125c storage temperature ............................................................................................................ ................... -65c to +150c voltage on v dd with respect to v ss .......................................................................................................... -0.3v to +5.5v voltage on all other pins with respect to v ss (except v dd )............................................................. -0.6v to (v dd + 0.6v) total power dissipation ( note ) .............................................................................................................................7 00 mw maximum current out of v ss pin ........................................................................................................................... 150 ma maximum current into v dd pin ........................................................................................................................... ...125 ma input clamp current, i ik (v i < 0 or v i > v dd ) ............................................................... ....................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................... ............................................... 20 ma maximum output current sunk by any output pin .................................................................................. ..................25 ma maximum output current sourced by any output pin ............................................................................... ................25 ma note: power dissipation is calculated as follows: p dis = v dd x {i dd - i oh } + {(v dd - v oh ) x i oh } + (v ol x i ol ) ? note: the graphs and tables provided following this note ar e a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics li sted herein are not tested or guaranteed. in some graphs or tabl es, the data presented may be outside the specified operating range (e.g., out- side specified power supply range) and therefore outside the warranted range.
MCP23017/mcp23s17 ds21952b-page 28 ? 2007 microchip technology inc. 2.1 dc characteristics dc characteristics operating conditions (unless otherwise indicated): 1.8v v dd 5.5v at -40 c t a +85 c (i-temp) 4.5v v dd 5.5v at -40 c t a +125 c (e-temp) (note 1) param no. characteristic sym min typ (note 1( max units conditions d001 supply voltage v dd 1.8 ? 5.5 v d002 v dd start voltage to ensure power-on reset v por ?v ss ?v d003 v dd rise rate to ensure power-on reset sv dd 0.05 ? ? v/ms design guidance only. not tested. d004 supply current i dd ? ? 1 ma scl/sck = 1 mhz d005 standby current i dds ??1a ? ? 3 a 4.5v-5.5v @ +125 c (note 1) input low voltage d030 a0, a1 (ttl buffer) v il v ss ?0.15v dd v d031 cs , gpio, scl/sck, sda, a2, reset (schmitt trigger) v ss ?0.2v dd v input high voltage d040 a0, a1 (ttl buffer) v ih 0.25 v dd + 0.8 ? v dd v d041 cs , gpio, scl/sck, sda, a2, reset (schmitt trigger) 0.8 v dd ?v dd v for entire v dd range input leakage current d060 i/o port pins i il ??1av ss v pin v dd output leakage current d065 i/o port pins i lo ??1av ss v pin v dd d070 gpio weak pull-up current i pu 40 75 115 a v dd = 5v, gp pins = v ss ?40c t a +85c output low-voltage d080 gpio v ol ??0.6vi ol = 8.0 ma, v dd = 4.5v int ? ? 0.6 v i ol = 1.6 ma, v dd = 4.5v so, sda ? ? 0.6 v i ol = 3.0 ma, v dd = 1.8v sda ? ? 0.8 v i ol = 3.0 ma, v dd = 4.5v output high-voltage d090 gpio, int, so v oh v dd ? 0.7 ? ? v i oh = -3.0 ma, v dd = 4.5v v dd ? 0.7 ? ? i oh = -400 a, v dd = 1.8v capacitive loading specs on output pins d101 gpio, so, int c io ? ? 50 pf d102 sda c b ??400pf note 1: this parameter is characterized, not 100% tested.
? 2007 microchip technology inc. ds21952b-page 29 MCP23017/mcp23s17 figure 2-1: load cond itions for device timing specifications figure 2-2: reset and device reset timer timing 135 pf 1k v dd scl and sda pin MCP23017 50 pf pin v dd reset internal reset 34 output pin 32 30
MCP23017/mcp23s17 ds21952b-page 30 ? 2007 microchip technology inc. table 2-1: device reset specifications figure 2-3: i 2 c? bus start/stop bits timing figure 2-4: i 2 c? bus data timing ac characteristics operating conditions (unless otherwise indicated): 1.8v v dd 5.5v at -40 c t a +85 c (i-temp) 4.5v v dd 5.5v at -40 c t a +125 c (e-temp) (note 1) param no. characteristic sym min typ (1) max units conditions 30 reset pulse width (low) t rstl 1??s 32 device active after reset high t hld ?0?nsv dd = 5.0v 34 output high-impedance from reset low t ioz ?? 1 s note 1: this parameter is characterized, not 100% tested. 91 93 scl sda start condition stop condition 90 92 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
? 2007 microchip technology inc. ds21952b-page 31 MCP23017/mcp23s17 table 2-2: i 2 c? bus data requirements i 2 c? ac characteristics operating conditions (unless otherwise indicated): 1.8v v dd 5.5v at -40 c t a +85 c (i-temp) 4.5v v dd 5.5v at -40 c t a +125 c (e-temp) (note 1) r pu (scl, sda) = 1 k , c l (scl, sda) = 135 pf param no. characteristic sym min typ max units conditions 100 clock high time: t high 100 khz mode 4.0 ? ? s 1.8v?5.5v (i-temp) 400 khz mode 0.6 ? ? s 2.7v?5.5v (i-temp) 1.7 mhz mode 0.12 ? ? s 4.5v?5.5v (e-temp) 101 clock low time: t low 100 khz mode 4.7 ? ? s 1.8v?5.5v (i-temp) 400 khz mode 1.3 ? ? s 2.7v?5.5v (i-temp) 1.7 mhz mode 0.32 ? ? s 4.5v?5.5v (e-temp) 102 sda and scl rise time: t r (note 1) 100 khz mode ? ? 1000 ns 1.8v?5.5v (i-temp) 400 khz mode 20 + 0.1 c b (2) ? 300 ns 2.7v?5.5v (i-temp) 1.7 mhz mode 20 ? 160 ns 4.5v?5.5v (e-temp) 103 sda and scl fall time: t f (note 1) 100 khz mode ? ? 300 ns 1.8v?5.5v (i-temp) 400 khz mode 20 + 0.1 c b (2) ? 300 ns 2.7v?5.5v (i-temp) 1.7 mhz mode 20 ? 80 ns 4.5v?5.5v (e-temp) 90 start condition setup time: t su : sta 100 khz mode 4.7 ? ? s 1.8v?5.5v (i-temp) 400 khz mode 0.6 ? ? s 2.7v?5.5v (i-temp) 1.7 mhz mode 0.16 ? ? s 4.5v?5.5v (e-temp) 91 start condition hold time: t hd : sta 100 khz mode 4.0 ? ? s 1.8v?5.5v (i-temp) 400 khz mode 0.6 ? ? s 2.7v?5.5v (i-temp) 1.7 mhz mode 0.16 ? ? s 4.5v?5.5v (e-temp) 106 data input hold time: t hd : dat 100 khz mode 0 ? 3.45 s 1.8v?5.5v (i-temp) 400 khz mode 0 ? 0.9 s 2.7v?5.5v (i-temp) 1.7 mhz mode 0 ? 0.15 s 4.5v?5.5v (e-temp) 107 data input setup time: t su : dat 100 khz mode 250 ? ? ns 1.8v?5.5v (i-temp) 400 khz mode 100 ? ? ns 2.7v?5.5v (i-temp) 1.7 mhz mode 0.01 ? ? s 4.5v?5.5v (e-temp) 92 stop condition setup time: t su : sto 100 khz mode 4.0 ? ? s 1.8v?5.5v (i-temp) 400 khz mode 0.6 ? ? s 2.7v?5.5v (i-temp) 1.7 mhz mode 0.16 ? ? s 4.5v?5.5v (e-temp) note 1: this parameter is characterized, not 100% tested. 2: c b is specified to be from 10 to 400 pf.
MCP23017/mcp23s17 ds21952b-page 32 ? 2007 microchip technology inc. figure 2-5: spi input timing 109 output valid from clock: t aa 100 khz mode ? ? 3.45 s 1.8v?5.5v (i-temp) 400 khz mode ? ? 0.9 s 2.7v?5.5v (i-temp) 1.7 mhz mode ? ? 0.18 s 4.5v?5.5v (e-temp) 110 bus free time: t buf 100 khz mode 4.7 ? ? s 1.8v?5.5v (i-temp) 400 khz mode 1.3 ? ? s 2.7v?5.5v (i-temp) 1.7 mhz mode n/a ? n/a s 4.5v ? 5.5v (e-temp) bus capacitive loading: c b 100 khz and 400 khz ? ? 400 pf note 1 1.7 mhz ? ? 100 pf note 1 input filter spike suppression (sda and scl) t sp 100 khz and 400 khz ? ? 50 ns 1.7 mhz ? ? 10 ns spike suppression off table 2-2: i 2 c? bus data requirements (continued) i 2 c? ac characteristics operating conditions (unless otherwise indicated): 1.8v v dd 5.5v at -40 c t a +85 c (i-temp) 4.5v v dd 5.5v at -40 c t a +125 c (e-temp) (note 1) r pu (scl, sda) = 1 k , c l (scl, sda) = 135 pf param no. characteristic sym min typ max units conditions note 1: this parameter is characterized, not 100% tested. 2: c b is specified to be from 10 to 400 pf. cs sck si so 1 5 4 7 6 3 10 2 lsb in msb in high-impedance 11 mode 1,1 mode 0,0
? 2007 microchip technology inc. ds21952b-page 33 MCP23017/mcp23s17 figure 2-6: spi output timing cs sck so 8 13 msb out lsb out 2 14 don?t care si mode 1,1 mode 0,0 9 12 table 2-3: spi interface ac characteristics spi interface ac characteristics operating conditions (unless otherwise indicated): 1.8v v dd 5.5v at -40 c t a +85 c (i-temp) 4.5v v dd 5.5v at -40 c t a +125 c (e-temp) (note 1) param no. characteristic sym min typ max units conditions clock frequency f clk ? ? 5 mhz 1.8v?5.5v (i-temp) ? ? 10 mhz 2.7v?5.5v (i-temp) ? ? 10 mhz 4.5v?5.5v (e-temp) 1cs setup time t css 50 ? ? ns 2cs hold time t csh 100 ? ? ns 1.8v?5.5v (i-temp) 50 ? ? ns 2.7v?5.5v (i-temp) 50 ? ? ns 4.5v?5.5v (e-temp) 3cs disable time t csd 100 ? ? ns 1.8v?5.5v (i-temp) 50 ? ? ns 2.7v?5.5v (i-temp) 50 ? ? ns 4.5v?5.5v (e-temp) 4 data setup time t su 20 ? ? ns 1.8v?5.5v (i-temp) 10 ? ? ns 2.7v?5.5v (i-temp) 10 ? ? ns 4.5v?5.5v (e-temp) 5 data hold time t hd 20 ? ? ns 1.8v?5.5v (i-temp) 10 ? ? ns 2.7v?5.5v (i-temp) 10 ? ? ns 4.5v?5.5v (e-temp) 6 clk rise time t r ?? 2 s note 1 7 clk fall time t f ?? 2 s note 1 8 clock high time t hi 90 ? ? ns 1.8v?5.5v (i-temp) 45 ? ? ns 2.7v?5.5v (i-temp) 45 ? ? ns 4.5v?5.5v (e-temp) note 1: this parameter is characterized, not 100% tested.
MCP23017/mcp23s17 ds21952b-page 34 ? 2007 microchip technology inc. figure 2-7: gpio and int timing 9 clock low time t lo 90 ? ? ns 1.8v?5.5v (i-temp) 45 ? ? ns 2.7v?5.5v (i-temp) 45 ? ? ns 4.5v?5.5v (e-temp) 10 clock delay time t cld 50 ? ? ns 11 clock enable time t cle 50 ? ? ns 12 output valid from clock low t v ? ? 90 ns 1.8v?5.5v (i-temp) ? ? 45 ns 2.7v?5.5v (i-temp) ? ? 45 ns 4.5v?5.5v (e-temp) 13 output hold time t ho 0??ns 14 output disable time t dis ??100ns table 2-3: spi interface ac characteristics (continued) spi interface ac characteristics operating conditions (unless otherwise indicated): 1.8v v dd 5.5v at -40 c t a +85 c (i-temp) 4.5v v dd 5.5v at -40 c t a +125 c (e-temp) (note 1) param no. characteristic sym min typ max units conditions note 1: this parameter is characterized, not 100% tested. 50 scl/sck sda/si in gpn pin d0 d1 lsb of data byte zero during a write or read int pin int pin active 51 command, depending on parameter output gpn pin input inactive 53 52 register loaded
? 2007 microchip technology inc. ds21952b-page 35 MCP23017/mcp23s17 table 2-4: gp and int pins ac characteristics operating conditions (unless otherwise indicated): 1.8v v dd 5.5v at -40 c t a +85 c (i-temp) 4.5v v dd 5.5v at -40 c t a +125 c (e-temp) (note 1) param no. characteristic sym min typ max units conditions 50 serial data to output valid t gpov ??500ns 51 interrupt pin disable time t intd ??600ns 52 gp input change to register valid t gpiv ??450ns 53 ioc event to int active t gpint ??600ns glitch filter on gp pins t glitch ??150ns note 1 note 1: this parameter is characterized, not 100% tested
MCP23017/mcp23s17 ds21952b-page 36 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21952b-page 37 MCP23017/mcp23s17 3.0 packaging information 3.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 28-lead soic yywwnnn example: 28-lead pdip (skinny dip) example: xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx 28-lead ssop yywwnnn xxxxxxxxxxxx xxxxxxxxxxxx example: 0648256 MCP23017 28-lead qfn example: e/ss^^ 3 e xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnn MCP23017 -e/sp^^ 0648256 3 e 0648256 MCP23017 -e/so^^ 3 e xxxxxxxx xxxxxxxx yywwnnn 23017 e/ml ^^ 0648256 3 e
MCP23017/mcp23s17 ds21952b-page 38 ? 2007 microchip technology inc. 28-lead skinny plastic dual in-line (sp) ? 300 mil body [spdip] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 28 pitch e .100 bsc top to seating plane a ? ? .200 molded package thickness a2 .120 .135 .150 base to seating plane a1 .015 ? ? shoulder to shoulder width e .290 .310 .335 molded package width e1 .240 .285 .295 overall length d 1.345 1.365 1.400 tip to seating plane l .110 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .040 .050 .070 lower lead width b .014 .018 .022 overall row spacing eb ? ? .430 note 1 n 12 d e1 e b c e l a2 e b b1 a1 a 3 microchip technology drawing c04-070b
? 2007 microchip technology inc. ds21952b-page 39 MCP23017/mcp23s17 28-lead plastic quad flat, no lead package (ml) ? 6x6 mm body [qfn] with 0.55 mm contact length notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. package is saw singulated. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 28 pitch e 0.65 bsc overall height a 0.80 0.90 1.00 standoff a1 0.00 0.02 0.05 contact thickness a3 0.20 ref overall width e 6.00 bsc exposed pad width e2 3.65 3.70 4.20 overall length d 6.00 bsc exposed pad length d2 3.65 3.70 4.20 contact width b 0.23 0.30 0.35 contact length l 0.50 0.55 0.70 contact-to-exposed pad k 0.20 ? ? d exposed d2 e b k e2 e l n note 1 1 2 2 1 n a a1 a 3 top view bottom view pad microchip technology drawing c04-105b
MCP23017/mcp23s17 ds21952b-page 40 ? 2007 microchip technology inc. 28-lead plastic small outline (so) ? wide, 7.50 mm body [soic] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millmeters dimension limits min nom max number of pins n 28 pitch e 1.27 bsc overall height a ? ? 2.65 molded package thickness a2 2.05 ? ? standoff a1 0.10 ? 0.30 overall width e 10.30 bsc molded package width e1 7.50 bsc overall length d 17.90 bsc chamfer (optional) h 0.25 ? 0.75 foot length l 0.40 ? 1.27 footprint l1 1.40 ref foot angle top 0 ? 8 lead thickness c 0.18 ? 0.33 lead width b 0.31 ? 0.51 mold draft angle top 5 ? 15 mold draft angle bottom 5 ? 15 c h h l l1 a2 a1 a note 1 12 3 b e e e1 d n microchip technology drawing c04-052b
? 2007 microchip technology inc. ds21952b-page 41 MCP23017/mcp23s17 28-lead plastic shrink small outline (ss) ? 5.30 mm body [ssop] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.20 mm per side. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 28 pitch e 0.65 bsc overall height a ? ? 2.00 molded package thickness a2 1.65 1.75 1.85 standoff a1 0.05 ? ? overall width e 7.40 7.80 8.20 molded package width e1 5.00 5.30 5.60 overall length d 9.90 10.20 10.50 foot length l 0.55 0.75 0.95 footprint l1 1.25 ref lead thickness c 0.09 ? 0.25 foot angle 0 4 8 lead width b 0.22 ? 0.38 l l1 c a2 a1 a e e1 d n 1 2 note 1 b e microchip technology drawing c04-073b
MCP23017/mcp23s17 ds21952b-page 42 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21952b-page 39 MCP23017/mcp23s17 appendix a: revision history revision b (february 2007) 1. changed byte and sequential read in figure 1-1 from ?r? to ?w?. 2. table 2-4, param no. 51 and 53: changed from 450 to 600 and 500 to 600, respecively. 3. added disclaimers to package outline drawings. 4. updated package outline drawings. revision a (june 2005) ? original release of this document.
MCP23017/mcp23s17 ds21952b-page 40 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21952b-page 41 MCP23017/mcp23s17 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device MCP23017: 16-bit i/o expander w/i 2 c? interface MCP23017t: 16-bit i/o expander w/i 2 c interface (tape and reel) mcp23s17: 16-bit i/o expander w/spi interface mcp23s17t: 16-bit i/o expander w/spi interface (tape and reel) temperature range e = -40 c to +125 c (extended) package ml = plastic quad, flat no leads (qfn), 28-lead sp = plastic dip (300 mil body), 28-lead so = plastic soic (300 mil body), 28-lead ss = ssop, (209 mil body, 5.30 mm), 28-lead part no. x /xx package temperature range device examples: a) MCP23017-e/sp: extended temp., 28ld pdip package. b) MCP23017-e/so: extended temp., 28ld soic package. c) MCP23017t-e/so: tape and reel, extended temp., 28ld soic package. d) MCP23017-e/ss: extended temp., 28ld ssop package. e) MCP23017t-e/ss: tape and reel, extended temp., 28ld ssop package. a) mcp23s17-e/sp: extended temp., 28ld pdip package. b) mcp23s17-e/so: extended temp., 28ld soic package. c) mcp23s17t-e/so: tape and reel, extended temp., 28ld soic package. d) mcp23s17-e/ss: extended temp., 28ld ssop package. e) mcp23s17t-e/ss: tape and reel, extended temp., 28ld ssop package. ?
MCP23017/mcp23s17 ds21952b-page 42 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21952b-page 43 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, linear active thermistor, migratable memory, mxdev, mxlab, ps logo, seeval, smartsensor and the embedded control solutions company are registered trademarks of microc hip technology incorporated in the u.s.a. analog-for-the-digital age, a pplication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, real ice, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwar e or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona, gresham, oregon and mountain view, california. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development syst ems is iso 9001:2000 certified.
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